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Silicon Labs /BGM220SC12WGA /MODEM_S /PRE

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Interpret as PRE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BASE0BASEBITS 0 (OUTER)PRESYMB4FSK 0PREERRORS 0 (DSSSPRE)DSSSPRE 0 (FSK2)SYNCSYMB4FSK 0TXBASES

PRESYMB4FSK=OUTER, SYNCSYMB4FSK=FSK2

Description

No Description

Fields

BASE

Preamble base
BASEBITS

BASE bits
PRESYMB4FSK

Preamble symbols 4-FSK

0 (OUTER): Symbols corresponding to +/- 3dev.

1 (INNER): Symbols corresponding to +/- dev.
PREERRORS

Preamble errors
DSSSPRE

DSSS preamble
SYNCSYMB4FSK

Sync symbols 4FSK

0 (FSK2): The syncword is 2FSK modulated. Each bit in SYNCn is encoded as a positive or negative deviation. The deviation is controlled by PRESYMB4FSK.

1 (FSK4): The syncword is 4FSK modulated. Every two bits in SYNCn are encoded as a 4FSK symbol.
TXBASES

TX bases

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data